Ferroelectric memory device having two columns of memory cells precharged to separate voltages

ABSTRACT

Since a ferroelectric memory device cannot employ a VCC/2 precharge scheme widely used in DRAM, its array noise and power consumption are large. Further, a ferroelectric capacitor is deteriorated in its characteristics due to its fatigue and imprint. To avoid this, data line pairs are precharged to two voltages VCC and VSS. As a result, a voltage on a data line in a memory cell array MCA varies symmetrically with respect to VCC/2 as its center to thereby reduce the array noise. Further, when early sense and early precharge operations are carried out based on charge share between data lines of different precharge voltages, the power consumption can be reduced. Furthermore, when the precharge voltages are switched for respective data lines, reverse and non-reverse polarization are alternately carried out in the ferroelectric capacitor in the memory cell to suppress its fatigue and imprint.

TECHNICAL FIELD

The present invention relates to a ferroelectric memory device. And moreparticularly, the invention relates to a ferroelectric memory devicehaving memory cells each of which is made up of a capacitor with aninsulating film of ferroelectric material and a MOS transistor.

BACKGROUND ART

As a nonvolatile memory realizing high-speed write operation, muchattention has been recently focused on a ferroelectric memory which usesa ferroelectric capacitor. In particular, a memory of such a type thateach memory cell is made up of a capacitor with an insulating film offerroelectric material and a MOS transistor and a constant voltage isapplied to one of electrodes of the capacitor called a plate has apossibility of being able to realize a nonvolatile memory with nearlythe same operating speed and area as those of a dynamic random accessmemory (DRAM). An example of a basic arrangement of such a prior artferroelectric memory is shown in FIG. 36. In the drawing, referencesymbol MC denotes a memory cell, which is made up of a ferroelectriccapacitor with an insulating film of ferroelectric material such as PZTand an NMOS transistor. The remanent polarization of the ferroelectriccapacitor stores information. The ferroelectric capacitor is connectedat its one end to the NMOS transistor and at the other end (plateelectrode) to 1/2 voltage (VCC/2) corresponding to half of a sourcevoltage VCC. For simplicity, only one memory cell MC is illustrated inthe illustrated example, but actually a plurality of such memory cellsare connected to each of a pair Dt and Db of data lines and are selectedby a word line W for data transfer to the data-line pair Dt or Db.Although omitted for simplicity in the drawing, a dummy cell is actuallyprovided to each of the data-line pair Dt and Db. Reference symbol PCdenotes a precharge circuit which precharges the data-line pair Dt andDb to a ground voltage VSS. Reference symbol SA denotes a senseamplifier which detects voltages of the data-line pair Dt and Db andamplifies the voltages differentially. Further, though omitted forsimplicity in the drawing, a switch is actually provided to the senseamplifier for signal transfer to or from external.

The operation of the above arrangement will be explained with use of atiming chart shown in FIG. 37. In a standby state, a control signal FPCcauses the precharge circuit PC to be put in its ON state, so that thedata-line pair Dt and Db are precharged to the ground voltage VSS, thatis, are in a so-called VSS precharge state. In operation, the controlsignal FPC causes the precharge circuit PC to be turned OFF. Thus whenthe word line W has a selected-word-line voltage VCH, the memory cell MCis selected. This causes an NMOS transistor in the memory cell MC to beturned ON, so that a voltage of VCC/2 corresponding to a difference involtage between a data line Dt and a plate electrode is applied to theferroelectric capacitor, whereby the remanent polarization is read outas charge to the data line Dt. This varies the voltage on the data lineDt and then a control signal FSA activates the sense amplifier SA, whichin turn amplifies the voltage of the data line D with positive feedbackto sense data. Though not illustrated in FIG. 37, when the data sensedby the sense amplifier SA is output externally, read operation iscarried out. Further, when the voltage of the data line is used as awrite voltage in accordance with externally entered data, writeoperation is carried out. When the word line W is lowered to turn OFFthe NMOS transistor in the memory cell MC, rewrite operation to thememory cell MC is carried out. Thereafter, the control signal FSA stopsthe operation of the sense amplifier SA, the control signal FPC turns ONa precharging switch, thus returning the current state to the standbymode.

The operation of the ferroelectric capacitor in the standby mode will beexplained with use of a hysteresis characteristic shown in FIG. 38. Inthe drawing, horizontal axis denotes a voltage applied to theferroelectric capacitor with the voltage of the plate electrode as areference, and vertical axis denotes a charge amount stored in theferroelectric capacitor including polarization. In such a condition thatno voltage is applied to the ferroelectric capacitor in the standbystate, the ferroelectric capacitor retains remanent polarization andtakes a position of either point PS0 or PS1 in FIG. 38 depending on data"0" or "1" stored in the capacitor. When it is desired to read out asignal from the memory cell MC to the data line D, the data line D isprecharged to -VCC/2 with the voltage of the plate electrode as areference, so that a data-line capacitance CD is represented by loadlines LL0 and LL1 having a gradient of -CD in FIG. 38. Intersections ofthe load lines and hysteresis characteristics are points which theferroelectric capacitor takes in its read mode. Meanwhile, the writeoperation is carried out when the capacitors takes a point PW0 or PW1 inFIG. 38 with the data line D having the voltage of VSS or VCC.

As has been explained above, in the ferroelectric memory device, thevoltage is applied to the ferroelectric capacitor to cause the reversepolarization to generate charge on the data line.

The following schemes which relate to the present application and aredirected to DRAMs have been disclosed.

Disclosed in JP-A-62-180591 is a scheme of dividing a precharge voltageof a data-line pair into two in order to reduce array noise.

Also disclosed in JP-A-5-135580 is a scheme of transferring chargebetween sense amplification groups in order to reduce a charge amountconsumed in rewrite and precharge operation.

Further disclosed in JP-A-4-184787 is a scheme of dividing a prechargevoltage of a data-line pair in a memory cell array into two to transfercharge between two data-line pairs. The present application will beexplained in association with these schemes.

DISCLOSURE OF INVENTION

In a ferroelectric memory device, in order to generate a signal voltageon a data line, a voltage must be applied to a ferroelectric capacitor.Thus, when a plate is set to have a constant voltage, it is impossibleto employ the scheme which reads out a signal with the data lineprecharged to VCC/2 and is widely used in DRAM fields, that is, aso-called VCC/2 precharge scheme. And the ferroelectric memory devicealso involves first to third problems which follow, when compared to aDRAM of the above VCC/2 precharge scheme.

First, the device has a large array noise. More specifically, aferroelectric memory employs a VSS precharge scheme (or VCC prechargescheme). Thus a signal is read out from one memory cell in all datalines, the voltage varies from VSS toward a higher level (from VCCtoward a lower level in the vcc precharge scheme). For this reason,large coupling noise takes place in no-selected word lines or wellscoupled capacitively with them. The noise is again capacitively coupledwith the data lines to fluctuate the voltages of the data lines.Meanwhile, when a voltage at a storage-node in a selected memory celldrops, a plate voltage is lowered through a ferroelectric capacitor.This a voltage applied to the ferroelectric capacitor in the memory cellto becomes small, so that a part of the remanent polarization offerroelectric material to be read out as charge becomes small in amount,thus decreasing an S/N ratio. In the VSS precharge scheme, when avoltage between the data-line pair is amplified by a sense amplifier,one of the voltages of the data lines in pair is charged to VCC by thesense amplifier with a large variation, whereas the other voltage isdischarged to VSS with a small variation. For this reason, greatcoupling noise takes place in all nodes capacitively coupled with thedata-line pair, increasing the voltage. The noise is again capacitivelycoupled with the data lines so that differences in the magnitude ofcoupling capacitance between the data line pairs result in differentialnoise, thus reducing the S/N ratio. For such noise, DRAM is described indetail in a book entitled "Advanced Electronics I-9, Ultra LSIMemories", written by Kiyoo Itoh, issued from Baifuukan, 1994, Chapter3. The discussion in the book also holds true for the ferroelectricmemory. Further, the voltage of the data line discharged to VSS isboosted due to coupling, the MOS transistor of the memory cell connectedto the data line discharged to VSS is conducted so that VSS is input tothe ferroelectric capacitor, with a danger of destroying thepolarization data.

Second, power consumption is great. Either one of the data lines Dt andDb in pair is charged to VCC from VSS during its amplification, and isdischarged again to VSS during its precharge operation. The amount ofcharge then consumed is CD×VCC per data line pair, when the data linecapacitance is CD. In the VCC/2 precharge scheme, one of the data linesin pair is charged from VCC/2 to VCC, the other is discharged from VCC/2to VSS, and precharge is carried out through charge share between thedata lines in pair. Therefore, a consumed charge amount per data-linepair is CD×VCC/2. Thus the VSS precharge scheme requires a powernecessary for charge and discharge of the data lines to be twice as highas that of the VCC/2 precharge scheme.

Third, the characteristics of the ferroelectric capacitor are largelydeteriorated by its fatigue and imprint. When read operation is carriedout in the VSS precharge mode, the polarization direction of theferroelectric capacitor having "1" so far written therein is reversed.Further, since VCC is applied to rewrite "1", the polarization directionis again reversed. The repetition of the above operation results incharacteristic deterioration caused by the fatigue. Meanwhile, therepetitive application of VSS results in that the characteristics of thecapacitor having "0" written therein are deteriorated by the imprint.That is, the fatigue or imprint becomes remarkable depending on thewritten data. Rewrite operation is carried out for all the memory cellson the selected word line and the read operation is generally carriedout more frequently than the reverse write operation, with the resultthat the same data is often repetitively written. This leads to theaforementioned fatigue and imprint phenomena.

It is an object of the present invention to solve problems in the aboveprior art ferroelectric memory device.

A first object of the present invention is to realize a high S/N ratioand stable operation by minimizing an array noise generated when amemory cell using a ferroelectric capacitor generates a signal voltage.

A second object is to realize a low necessary power by reducing theamount of charge consumed for rewriting and precharging.

A third object is to realize a high reliability by suppressing fatigueand imprint of a ferroelectric capacitor.

Other objects will become clear from description of embodiments whichfollow.

In accordance with the present invention, the above objects are attainedby providing a ferroelectric memory device which includes first andsecond memory cells (MC1) each having a ferroelectric capacitor with aninsulating film of ferroelectric material and having a transistorconnected to one of electrodes of the ferroelectric capacitor, a firstdata line (D0t) connected to said transistor of said first memory cell,a second data line (D1t) connected to said transistor of said secondmemory cell, word lines connected to control electrodes of thetransistors of said first and second memory cells, and first and secondsense amplifiers (SA0, SA1) provided as associated with said first andsecond data lines; and which further comprises a first precharge circuit(PC0) for connecting said first data line to a first precharge potential(Vss); and a second precharge circuit (PC1) for connecting said seconddata line to a second precharge potential (Vcc); and wherein a potential(Vcc/2) of the other electrodes of said ferroelectric capacitors of saidfirst and second memory cells is set to be between said first and secondprecharge potentials.

More desirably, a difference between the potential of the otherelectrodes of said ferroelectric capacitors and said first prechargepotential is equal to a difference between the potential of the otherelectrode of said ferroelectric capacitors and said second prechargepotential. That is, an average of the first and second prechargepotentials is set at a voltage close to an average of a write voltage of"1" and a write voltage of "0". More in detail, the above first to thirdobjects are attained by using first to third means which followrespectively.

The first means comprises word lines connected to control electrodes oftransistors in said first and second memory cells (refer to FIGS. 1 and2). Thereby noise from the first data line and noise from the seconddata line are cancelled each other to cancel noise toward the wordlines, thus attaining the first object.

A scheme of dividing the precharge voltages into two in DRAM isdisclosed in JP-A-62-180591 or JP-A-4184787. When a similar scheme tothe above is used for such a ferroelectric memory device as to requireVcc precharge or Vss precharge, there can be satisfied an essentialrequirement inherent in a ferroelectric memory device that a voltage beapplied to a ferroelectric capacitor at word-line activation. Withrespect to DRAM, it is common sense that, when factors including S/Nratio, power consumption and operational speed are generally considered,a VCC/2 precharge scheme is excellent. In such a ferroelectric memorydevice that a plate voltage is set to be constant, however, since theVCC/2 precharge scheme cannot be employed, such a scheme becomeseffective means.

The second means comprises:

first and second memory cells each including a ferroelectric capacitorwith an insulating film of ferroelectric material and including atransistor connected to one of electrodes of the ferroelectriccapacitor;

first and second data lines (D0tS, D0TC) connected to said correspondingfirst and second memory cells;

a first precharge circuit (PC0S) for connecting said first data line toa first precharge potential;

a second precharge circuit (PC0C) for connecting said second data lineto a second precharge potential;

a first sense amplifier (SA0S) made up of two P-channel MOS transistorscross-coupled for detecting data from said first memory cell appearingon said first data line;

a second sense amplifier (SA0C) made up of two N-channel MOS transistorscross-coupled for detecting data from said second memory cell appearingon said second data line;

a first driving line (CSPS) for driving said first sense amplifier;

a second driving line (CSNC) for driving said second sense amplifier;and

a switch circuit (CSD) for allowing continuity between said first andsecond driving lines after potentials (Vss, Vcc) are supplied to saidfirst and second driving lines to put said first and second senseamplifiers in their non-driving state respectively and then the supplyis stopped (refer to FIGS. 20 and 21).

With the above arrangement, the second object is attained. A scheme ofperforming charge transfer between two groups of sense amplifiers inDRAM is disclosed in JP-A-5-135580. In this prior art, charge transferis carried out between the sense amplifier group after data lineamplification and the sense amplifier group for the next amplification.For this reason, this is effective when the sense amplifiers groups aresequentially activated in a given order as in the self-refresh operationof DRAM, but its applicable operation is limited. For example, when theidentical sense amplifier group is activated twice continuously, thisscheme cannot be used. Meanwhile, in the present means, since chargetransfer is carried out between the sense amplifier groups of differentprecharge voltages, this scheme can be applied to usual random accessoperation. Further, with respect to DRAM, JP-A-4-184787 discloses ascheme of grouping precharge voltages of a data line pair in a memorycell array into two for data transfer between two of data line pairs.When such a scheme is applied to a ferroelectric memory device, arequirement that a voltage be applied to a ferroelectric capacitor atword-line activation, can be attained. For such a ferroelectric memorydevice as not to employ the VCC/2 precharge scheme, this scheme iseffective means.

The third means comprises:

memory cells each including a ferroelectric capacitor with an insulatingfilm of ferroelectric material and including a transistor connected toone of electrodes of the ferroelectric capacitor;

a data line (D0t) connected to the memory cells; and

a precharge circuit (PC0) for precharging said data line to a first orsecond precharge potential, and wherein the potential (Vcc/2) of theother electrodes of said ferroelectric capacitors of said memory cellsis set to be between said first precharge potential (Vss) and saidsecond precharge potential (Vcc), and said precharge circuit alternatelyprecharges said data line with said first and second prechargepotentials (refer to FIG. 26).

Thereby, two sorts of Vss and Vcc precharge schemes can be applied witha high possibility to the identical memory cell, thus attaining thethird object.

Further, means corresponding to a combination of the above means enablessimultaneous attainment of a combination of the effects of the abovemeans.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary basic arrangement of a first embodiment.

FIG. 2 shows an exemplary arrangement of a memory array.

FIG. 3 is a basic operational timing chart of the first embodiment.

FIG. 4 is an exemplary arrangement which data-line pairs are grouped forevery 2 pairs with respect to precharge voltages.

FIG. 5 is an operational timing chart when the precharge voltages of thedata-line pairs are grouped for every 2 pairs.

FIG. 6 shows an exemplary structure of a precharge circuit using CMOSs.

FIG. 7 is an operational timing chart of the exemplary structure of theprecharge circuit using CMOSs.

FIG. 8 shows another exemplary arrangement of the memory array.

FIG. 9 shows an exemplary arrangement when a column decoder is shared bya plurality of memory arrays.

FIG. 10 shows an exemplary arrangement of a control circuit of I/O linepairs.

FIG. 11 is a read operation timing chart of the exemplary arrangement ofFIG. 9.

FIG. 12 is a write operation timing chart of the exemplary arrangementof FIG. 9.

FIG. 13 shows an exemplary arrangement when the input-line pairs areseparated from the output-line pairs.

FIG. 14 is an operational timing chart of the exemplary arrangement ofFIG. 13.

FIG. 15 a write operation timing chart of the exemplary arrangement ofFIG. 13.

FIG. 16 shows a part of an exemplary arrangement when sense amplifiersare positioned at both ends of a memory cell array.

FIG. 17 shows a continuation from the exemplary arrangement when senseamplifiers are positioned at both ends of a memory cell array.

FIG. 18 is a read operation timing chart of the exemplary arrangement ofFIGS. 16 and 17.

FIG. 19 is a write operation timing chart of the exemplary arrangementof FIGS. 16 and 17.

FIG. 20 shows an exemplary basic arrangement of a second embodiment.

FIG. 21 is a basic operational timing chart of the second embodiment.

FIG. 22 shows an exemplary arrangement of a sense amplifier drivingcircuit and a control circuit.

FIG. 23 is an operational timing chart of the exemplary arrangement ofFIG. 22.

FIG. 24 shows another exemplary arrangement of the sense amplifierdriving circuit and control circuit.

FIG. 25 is an operational timing chart of the exemplary arrangement ofFIG. 24.

FIG. 26 is an exemplary basic arrangement of a third embodiment.

FIG. 27 is a basic operational timing chart of the third embodiment.

FIG. 28 shows an exemplary arrangement of a combination of the third andfirst embodiments.

FIG. 29 is an operational timing chart of the exemplary arrangement ofFIG. 28.

FIG. 30 is an exemplary arrangement of a sense amplifier driving circuitin the third embodiment.

FIG. 31 is an operational timing chart of the exemplary arrangement ofFIG. 28.

FIG. 32 shows a part of an exemplary arrangement when sense amplifiersare positioned at both ends of a memory cell array in the thirdembodiment.

FIG. 33 shows another part of the exemplary arrangement when the senseamplifiers are positioned at both ends of the memory cell array in thethird embodiment.

FIG. 34 is a read operation timing chart of the exemplary arrangementsof FIGS. 32 and 33.

FIG. 35 is a write operation timing chart of the exemplary arrangementsof FIGS. 32 and 33.

FIG. 36 shows an exemplary basic arrangement of a prior art.

FIG. 37 shows a basic operational timing chart of the prior art.

FIG. 38 shows a hysteresis characteristic of a ferroelectric capacitor.

BEST MODE FOR CARRYING OUT THE INVENTION

First to third embodiments corresponding to the above first to thirdmeans will be explained.

[First Embodiment]

First, an embodiment of realizing the above first means will beexplained. A major part of an exemplary arrangement of the embodiment isshown in FIG. 1. This embodiment is featured in that precharge voltagesof data-line pairs in a memory cell array are divided into two.Connected to data-line pairs D0b and D0t, D1b and D1g, . . . areprecharge circuits PC0 PC1, . . . and sense amplifiers SA0, SA1, . . .Each of the precharge circuits is made up of 3 NMOS transistors.Supplied to the precharge circuits PC0 and PC2 is a ground voltage VSS,while supplied to the precharge circuits PC1 and PC3 is a source voltageVCC. Each of the sense amplifiers comprises a CMOS circuit which has thesame configuration as a circuit widely used as a DRAM sense amplifier.NMOS transistors of the sense amplifiers SA0 and SA2, . . . areconnected at their source terminals to the ground voltage VSS, whileNMOS transistors of the sense amplifiers SA1 and SA3, . . . areconnected at their source terminals to the source voltage VCC. Forsimplicity, I/O lines and I/O gates, etc. for data transfer to externaldevices are omitted.

Reference symbol MCA denotes a memory cell array which is formed, forexample, as shown by MCA1 in FIG. 2. A multiplicity of memory cells MC1susing a ferroelectric capacitor are provided at a desired intersectionof the data-line pairs D0b and D0t, D1b and D1t, . . . and the wordlines W0, W1, . . . This arrangement is the same as a so-calledfolded-data-line arrangement widely used in DRAM. The memory cell MC1 ismade up of, for example, an insulating film of ferroelectric materialsuch as lead zirconate titanate (PZT) and an NMOS transistor. Data isstored in the ferroelectric capacitor as remanent polarization. Theferroelectric capacitor is connected at its one electrode to the NMOStransistor and at the other electrode (plate electrode) to a node commonto a plurality of memory cells to receive an intermediate voltage VCC/2.This memory cell has a structure similar to a one-transistor,one-capacitor type memory cell generally used for DRAM. In this way, thememory cell is made up of one MOS transistor and one ferroelectriccapacitor to decrease a cell area, thus enabling its scaling. With thismemory cell array structure, since signal reading operation is carriedout only from one of data lines in pair, a mechanism for generating areference signal is necessary for performing differential amplificationby the sense amplifier. However, such a mechanism is omitted in thedrawing for simplicity. Means for generating the reference signal isdisclosed, for example, in JP-A-2-110893 or JP-A-6-302193.

The operation of this structure example will be explained with use of atiming chart shown in FIG. 3. In the standby state, the control signalFPC is VCH such that the NMOS transistors in the precharge circuits PC0,PC1, . . . are turned ON, the data-line pairs D0b and D0t, D2b and D2t,. . . are precharged to VSS, and the data-line pairs D1b and D1t, D3band D3t, . . . are precharged to VCC. That is, the data-line pairs areprecharged to VSS and VCC alternately for every other pair. Duringoperation, the control signal FPC causes the precharge circuits PC to beturned OFF. Thus, when the word line (W0 in FIG. 3) is set at aselected-word-line voltage VCH during selection, the memory cell MC1 isselected. At this time, the NMOS transistor in the selected memory cellMC1 is turned ON, a voltage corresponding to a difference between avoltage on the data line of the ferroelectric capacitor and the platevoltage VCC/2 is applied to the ferroelectric capacitor, and remanentpolarization of the capacitor is read onto the data line in the form ofcharge. At this time, the voltage of the data-line pairs D0b and D0t,D2b and D2t, . . . rise from VSS, while the voltage of the data-linepairs D1b and D1t, D3b and D3t, . . . falls. And when a sense amplifierdriving line CSP0 is set at VCC, the sense amplifiers SA0, SA2, . . .are activated; whereas, when a sense amplifier driving line CSN1 is setat VSS, the sense amplifiers SA1, SA3, . . . are activated todifferentially amplify the voltages of the respective data-line pairsfor data sense. At this time, the sense amplifier performs itsamplifying operation with positive feedback, whereby one of the datalines in each pair is amplified to VSS and the other is amplified toVCC. For the data-line pairs D0b and D0t, D2b and D2t, . . . , however,a swing in the voltage of the data lines amplified to VSS is small;whereas a swing in the voltage of the data lines amplified to VCC islarge. Conversely, for the data-line pairs D1b and D1t, D3b and D3t, . .. , a swing in the voltage of the data lines amplified to VSS is large;whereas a swing in the voltage of the data lines amplified to VCC issmall. When the data is externally transferred under a condition thatthe sense amplifier amplified the data, read operation is carried out.When the voltage of the data lines is controlled according to the dataexternally given, write operation is carried out. When the voltage ofthe word line W0 is lowered to turn OFF the NMOS transistor in thememory cell MC1, rewrite operation is carried out. Thereafter, the senseamplifier driving line CSP0 is set at VSS and sense amplifier drivingline CSN1 is set at VCC to stop the operation of the sense amplifier.And the control signal FPC causes the precharge circuit to be turned ONto return the current mode to the standby state. In this connection, thevoltage applied to the ferroelectric capacitor attenuates with a leakagecurrent flowing through the memory cell. In some cases, the intermediatevoltage VCC/2 is applied to the memory cell to set the voltage appliedto the ferroelectric capacitor at 0.

Through the operation explained above, the aforementioned first problemcan be solved in such a manner as will be explained below. That is, whena signal is read out from the memory cell as charge, with respect to thevoltages of the data-line pairs, the voltage of the data-line pairs D0band D0t, D2b and D2t, . . . is changed from VSS to its higher level;whereas, the voltage of the data-line pairs D1b and D1t, D3b and D3t, .. . is changed from VCC to its lower level. In other words, thesevoltages vary symmetrically with respect to the intermediate voltageVCC/2 as its center. For this reason, the non-selected word lines orwells have less coupling noise capacitively coupled with these voltages,since the coupling of the data-line pairs D0b and D0t, D2b and D2t, . .. and the coupling of the data-line pairs D1b and D1t, D3b and D3t, . .. cancel each other. Meanwhile, the voltage change of the storage nodein the selected memory cell also varies substantially symmetrically withrespect to the intermediate voltage VCC/2 as its center, the voltagechange of the plate is small. For this reason, the voltage applied tothe ferroelectric capacitor will not become small. When amplified by thesense amplifier, one of the data lines of the data-line pairs D0b andD0t, D2b and D2t, . . . is charged to VCC so that the voltage thereofchanges largely; whereas, the other of the data lines of the data-linepairs D1b and D1t, D3b and D3t, . . . is discharged to VSS so that thevoltage thereof changes largely. That is, even at this time, the voltagevaries symmetrically with respect to the intermediate voltage VCC/2 asits center. Accordingly, the node capacitively coupled with thedata-line pair is small. There is no possibility that the non-selectedword lines are boosted through the coupling. As mentioned above, in thepresent embodiment, the voltages of the data-line pairs varysymmetrically with respect to the intermediate voltage VCC/2 as itscenter, with the result that its array noise becomes small as in theVCC/2 precharge scheme widely used in DRAM.

Various modification examples and application examples will be explainedin the following.

FIG. 4 shows an example of arrangement when the data-line pair isprecharged alternately to VSS and VCC for every 2 pairs. As in theexemplary arrangement shown in FIG. 1, the precharge circuits PC0, PC1,. . . and the sense amplifiers SA0, SA1, . . . are connected to thedata-line pairs D0b and D0t, D1b and D1t, . . . respectively. The groundvoltage VSS is supplied to the precharge circuits PC0 and PC1, while thesource voltage VCC is supplied to the precharge circuits PC2 and PC3.Sources of NMOS transistors in the sense amplifiers SA0, SA1, . . . areconnected to the ground voltage VSS, while sources of PMOS transistorsin the sense amplifiers SA2, SA3, . . . are connected to the sourcevoltage VCC. The interconnections of the precharge circuits and senseamplifiers are repeated on every 4 circuit or amplifier basis. As inFIG. 1, I/O lines and I/O gates for data transfer to external areomitted in the drawing. Its operational timing shown in FIG. 5 issimilar to the operational timing shown in FIG. 3, except that the senseamplifier driving line CSN2 is driven like the sense amplifier drivingline CSN1 in FIG. 2. The voltage of the data-line pairs is prechargedalternately to VSS and VCC on every 2 pair basis. As a result, as viewedfrom the entire array, the voltage of the data-line pairs variessymmetrically with respect to the intermediate voltage VCC/2 as itscenter with less array noise.

With this exemplary arrangement, each two of the precharge circuits andsense amplifiers are connected to the same node. For this reason, theconnection from a control line to the MOS transistors can be commonlyrealized, thus facilitating its layout. Further, such an arrangement mayalso be employed that the precharge voltage is switched on every 4 or 8pair basis. In the case that the plate or non-selected word line wherecoupling noises are generated in the prior art arrangement has a highresistance, however, it is desirable to switch the precharge voltagefinely on every pair or two pair basis. It is because the noise becomeslarger as the data lines having symmetrically varying voltages arepositioned more apart therefrom.

FIG. 6 shows an exemplary arrangement when the data-line pair isprecharged to the source voltage VCC with use of a precharge circuit ofPMOS transistors. More specifically, a precharge circuit PCN0 made up ofNMOS transistors is connected to the data-line pair D0b and D0t, and theground voltage VSS is supplied to the circuit PCN0. On the other hand, aprecharge circuit PCP1 made up of PMOS transistors is connected to thedata-line pair D1b and D1t, and the source voltage VCC is supplied tothe circuit PCP1. NMOS transistors in a sense amplifier SA0 connected tothe data-line pair D0b and D0t are connected at their sources to theground voltage VSS; and PMOS transistors in the sense amplifiers SA2,SA3, . . . are connected at their sources to the source voltage VCC. Thestructure and interconnection of the precharge circuits and senseamplifiers are repeated on every two circuit/two amplifier basis. As inFIG. 1, I/O lines and I/O gates for data transfer to external devicesare omitted in the drawing. Its operational timing shown in FIG. 7 issimilar to the operational timing shown in FIG. 3, except that thevoltage of a control signal FPC0 of the precharge circuits varies fromthe ground voltage VSS down to the source voltage VCC and that a controlsignal FPC1 is a complementary form of the control signal FPC0. Thevoltage of the data-line pairs is precharged alternately to VSS and VCCon every pair basis, with a small array noise as in the arrangement ofFIG. 1.

Since the source voltage VCC is supplied from the precharge circuit PCusing the PMOS transistors, the precharge circuit can have a resistancesmaller than that of the precharge circuit using the NMOS transistors,whereby the precharging rate can be speeded up and a cycle time can beshortened. Further, since it becomes unnecessary to use the word voltageVCH as the control signal of the precharge circuit, the charge-pumpability of the boosting circuit can be lightened when it is desired toboost the source voltage VCC to supply the voltage VCH.

FIG. 8 shows another exemplary arrangement of the memory cell array as amemory cell array MCA2. The memory cell array MCA2 can be used in placeof the memory cell array MCA in FIG. 1. A memory cell MC2 in the memorycell array MCA2 is positioned at an intersection of word lines W0, W1, .. . and data-line pairs D0b and D0t, D1b and D1t, . . . The memory cellMC2 is made up of two ferroelectric capacitors and two NMO transistors.Data is complementarily stored in the two ferroelectric capacitors asremanent polarization thereof. Similarly to the memory cell MC1 in FIG.2, one electrodes of the ferroelectric capacitors are connected to theassociated NMOS transistors, and the other electrodes (plate electrodes)thereof are connected to the node common to the plurality of memorycells to receive the intermediate voltage VCC/2. Operational control iscarried out in such a manner as shown in FIG. 3 as in the case of usingthe memory cell array MCA1 of FIG. 2. With this memory cell array, sincesignals are read out to both of the data lines in pair, a mechanism forgenerating the reference signal can be made unnecessary, thus enablingthe operation with a high S/N ratio.

FIG. 9 shows an exemplary arrangement when a column decoder is commonlyused in a plurality of memory cell arrays, featuring two sets of I/Olines according to the precharge voltage of the data-line pairs. In thedrawing, reference symbols MCAL0 and MCAR0, MCAL1 and MCAR1, . . .denotes memory cell arrays which are each arranged, e.g., as shown byMCA1 in FIG. 2. Every two memory cell arrays share an amplifier partSAB0, SAB1, . . . which are each positioned between two memory cellarrays. Commonly provided to the pluralities of memory cell arrays andsense amplifier parts is a column decoder YDEC. A column select line YSis extended on the memory cell arrays. More specifically, each of thesense amplifier parts SAB0, SAB1, . . . is arranged as follows. Sharedgates SHLG0, SHLG1, . . . are connected to data-line pairs D0bL andD0tL, D1bL and D1tL, . . . in the memory cell arrays MCAL0, MCAL1, . . .Shared gate SHRG0, SHRG1, . . . are connected to data-line pairs D0bRand D0tR, D1bR and D1tR, . . . in the memory cell arrays MCAR0, MCAR1, .. . The shared gate plays a role of selecting the left and right dataline pairs. The precharge circuits PC0, PC1, . . . , sense amplifiersSA0, SA1, . . . , and I/O gates IOG0, IOG1, . . . are provided betweenthe shared gates SHLG0 and SHRG0, SHLG1 and SHRG1, . . . The prechargecircuits PC0, PC1, . . . and the sense amplifiers SA0, SA1, . . . havesuch a circuit configuration as shown in FIG. 1 respectively. The groundvoltage VSS is supplied to the precharge circuit PC0 and the sourcevoltage VCC is supplied to the precharge circuit PC1. NMOS transistorsin the sense amplifier SA0 are connected at their sources to the groundvoltage VSS, PMOS transistors in the sense amplifier SA1 are connectedat their sources to the source voltage VCC. The I/O gate IOG0 isconnected to I/O line pairs IO0b and IO0t, and the I/O gate IOG1 isconnected to I/O line pairs IO1b and IO1t. A column select line YS0 isprovided for two data-line pairs to control the I/O gates IOG0 and IOG1.The interconnection of the precharge circuits, sense amplifiers and I/Ogates for a control signal, etc. is repeated for two of the prechargecircuits, two of the sense amplifiers and two of the I/O gates.

Connected to the I/O line pairs are such control circuits as shown inFIG. 10. The I/O line precharge circuits IOPC0 and IOPC1, write circuitsWD0 and WD1, and main amplifiers MA0 and MA1 are connected to the I/Oline pairs IO0b and IO0t and IO1b and IO1t respectively. The groundvoltage VSS is supplied to the precharge circuit IOPC0, and the sourcevoltage VCC is supplied to the precharge circuit IOPC1.

The read operation of this arrangement will be explained with referenceto a timing chart shown in FIG. 11. The drawing shows when the word lineW0 is selected in the memory cell array MCAL0 to externally read signalsdetected by the sense amplifiers SA0 and SA1. In the standby state, thecontrol signal FPC causes the BNIS transistors in the precharge circuitsPC0, PC1, . . . and in the I/O line precharge circuits IOPC0 and IOPC1to be put in their ON state. Further, the control signals SHL and SHRare both at VCH, such that NMOS transistors in the shared gates SHLG0,SHLG1, . . . and in the shared gates SHRG0, SHRG1, . . . to be put intheir ON state. The data-line pairs D0bL and D0tL, D0bR and D0tR, . . .and the I/O line pair IO0b and IO0t are precharged to VSS, while thedata-line pairs D1bL and D1tL, D1bR and D1tR, . . . and the I/O linepair IO1b and IO1t are precharged to VCC. The control signal SHR is setat VSS to turn OFF the NMOS transistors in the shared gates SHRG0lSHRG1, . . . , thereby separating the memory cell array MCAR0 from thesense amplifier part SAB0. Further, the control signal FPC causesturning OFF of the precharge circuits PC0, PC1, . . . as well as the I/Oline precharge circuits IOPC0 and IOPC1. The data-line pairs D0bL andD0tL, D1bL and D1tL, . . . are floating. Meanwhile, the I/O line pairsIO0b and IO0t, IO1b and IO1t have a bias voltage determined by inputparts of the main amplifiers MA0 and MA1 when a local read-enable signalLREt is set at VCC. Thus, when the word line W0 is set at theselected-word-line voltage VCH, the memory cell MC1 is selected to readthe signal to the data-line pair. And the sense amplifier driving linesCSP0 and CSN1 activate the sense amplifiers SA0, SA1, . . . , wherebyone of the data-line pairs D0bL and D0tL, D1bL and D1tL, . . . is set atVCC and the other is set at VSS. In this case, the column select lineYS0 is selected by the column decoder YDEC to turn ON the I/O gate IOG0and to drive the I/O line pairs IO0b and IO0t, IO1b and IO1t by thesense amplifiers SA0 and SA1. This is detected by the main amplifiersMA0 and MA1 and output to output terminals DO0 and DO1 of the mainamplifiers, thus realizing the read operation. In this connection, bypreviously setting a local write-enable signal LWEt at VSS and localwrite-enable signal LWEb at VCC, the write circuits WD0 and WD1 are putin their high-impedance state. And the column select line YS0 islowered. When the word line W0 is lowered, rewrite operation to thememory cell MC1 is carried out. Thereafter, the control signal CSP isset at VSS and the control signal CSN1 is returned to VCC to stop theoperation of the sense amplifiers SA0, SA1, . . . The control signal FPCis then used to turn ON the precharge circuits PC0, PC1, . . . as wellas the I/O line precharge circuit IOPC0 and IOPC1. And the controlsignal SHR is used to turn ON the MNOS transistors in the shared gateSHRG0, to couple the memory cell array MCAR0 with the sense amplifierpart SAB0, thus returning it to the standby state.

Explanation will next be made as to the write operation with use of atiming chart shown in FIG. 12. The drawing shows when the word line W0is selected in the memory cell array MCAL0 to write a signal from thedata-line pairs D0bL and D0tL, and D1bL and D1tL. The write operationuntil the signal on the data-line pairs is detected is the same as theread operation shown in FIG. 11. The local write-enable signal LWEt isset at VCC and the local write-enable signal LWEb is set at VSS toactivate the write circuits WD0 and WD1, whereby the I/O line pairs IO0band IO0t, and IO1b and IO1t are driven according to input signals DI0and DI1. In this case, the local read-enable signal LREt is set at VSSto stop the operations of the main amplifiers MA0 and MA1. The columnselect line YS0 is selected by the column decoder YDEC to turn ON theI/O gate IOG0, whereby the I/O line pairs IO0b and Ioot, and IOlb andIO1t are coupled with the sense amplifiers SA0 and SA1 to put theamplifiers in a state corresponding to the write signal, thus realizingthe write operation. FIG. 12 shows when the sense amplifiers SA0 and SA1are both inverted. And the column select line YS0 is lowered and theword line W0 is also lowered to be returned to their standby state.

With the arrangement shown in FIG. 9, since the sense amplifier part isshared by its left and right memory cell arrays, an area of the senseamplifier part can be reduced. Further, by sharing the column decoder bythe plurality of sense amplifier parts, an area of the column decodercan be reduced. In this case, it is desirable to activate only a desiredsense amplifier part according to an address signal externally input andto maintain the nonselected sense amplifier part in the standby state.In this case, the I/O gate is turned ON by the column select line evenfor the non-selected sense amplifier part, so that the sense amplifieris coupled with the I/O line pair. When a separate pair of I/O lines areprovided for each precharge voltage as shown in FIG. 9, the I/O linepair and data-line pair possibly coupled with each other can bepreviously precharged to the same voltage, thus enabling prevention ofan unnecessary current from flowing therethrough.

FIG. 13 shows another exemplary arrangement when a column decoder isshared by a plurality of memory cell arrays. This arrangement isfeatured in that the common I/O line pair in the exemplary arrangementof FIG. 9 is separated into an input line pair and an output line pair.As in the exemplary arrangement shown in FIG. 9, sense amplifier partsSADB0, SADB1, . . . are located between two's of memory cell arraysMCAL0 and MCAR0, MCAL1 and MCAR1, . . . and shared thereby; and thus thecolumn decoder YDEC is commonly provided to the pluralities of memorycell arrays and sense amplifier parts. Details of the sense amplifierparts SADB0, SADB1, . . . are arranged as follows. Provided between theshared gates SHLG0 and SHRG0, SHLG1 and SHRG1, . . . are prechargecircuits PC0, PC1, . . . , sense amplifiers SA0, SA1, . . . , read gatesRG0, RG1, . . . , and write gates WG0, WG1, . . . The read gates RG0,RG1, . . . are connected to the output line pair ROb and Rot, and thewrite gates WG0, WG1, . . . are connected to I/O line pair WIb and Wit.In the read gate RG0, NMOS transistors connected at their sources to thecontrol signal LREb are of a depletion type. The interconnection of theprecharge circuits and sense amplifiers to the control signal, etc. isrepeated on a two-circuit and two-amplifier basis, but theinterconnection of the read and write gates is commonly used regardlessof the precharge voltage. The column select lines YS0, YS1, . . . areprovided for each pair of data lines.

Timing charts of the read and write operations are shown in FIGS. 14 and15 respectively. The drawings show when the word line W0 in the memorycell array MCAL0 is selected to read or write a signal from or in thedata-line pair D0tL and D0bL. These timing charts are the same as thetiming charts of FIGS. 11 and 12 up to detection of the signal on thedata-line pair by the sense amplifier and since setting of the columnselect line at VSS, but are different in the timing of driving thecolumn select line. As explained in IEEE Journal of Solid-StateCircuits, Vol. 26, No. 4, pp. 465-472, April, 1991, with regard to DRAM;a so-called direct sense scheme of separating input line pairs fromoutput line pairs to drive a column select line before activating asense amplifier can be employed to shorten an access time. The data-linepair D0tL and D0bL is previously precharged to VSS, but when a depletiontype of NMOS transistors are used in the read gate RG0, the signal canbe transmitted to the output-line pair before being amplified by thesense amplifier.

With this arrangement, the non-selected sense amplifiers are not coupledwith the input or output line pair and it is only required to use oneinput line pair and one out line pair.

FIGS. 16 and 17 shows an exemplary arrangement when a sense amplifier ispositioned at both sides of each of memory cell arrays. The arrangementis featured in that different precharge voltages are used for differentsense amplifier parts. Reference symbols MCB0, MCB1, MCB2, . . . denotememory cell arrays, which are each arranged, for example, as MCA1 inFIG. 2. Every two memory cell arrays share a sense amplifier part SAB0E,SAB1O, SAB2E, SAB30, . . . which are each provided between the twomemory cell arrays, while the sense amplifier parts provided at bothsides of each memory cell array perform sensing operation. A columndecoder YDEC is provided commonly to the pluralities of memory cellarrays and sense amplifier parts, and column select lines YS (such asYS0) are extended on the memory cell arrays. The interconnection of thesense amplifier parts is repeated on every two part basis. The senseamplifier part SAB1O is arranged as shown in FIG. 16 and is connected to0-th, second, . . . data line pairs in the memory cell arrays MCB0 andMCB1. Meanwhile, the sense amplifier part SAB2E is arranged as shown inFIG. 17 and is connected to first, third, . . . data line pairs in thememory cell arrays MCB1 and MCB2. Reference symbols SHLG0, SHRG0, SHLG1and SHRG1 denote shared gates, IOG0 and IOG1 denote I/O gates, eachhaving such a circuit configuration as shown in FIG. 9. Further,reference symbols PC0 and PC1 denote precharge circuits, SA0 and SA1denote sense amplifiers, each having such a circuit configuration asshown in FIG. 1.

The read and write operations are carried out as shown in FIGS. 18 and19 respectively. The drawings show when the word line W0 is selected inthe memory cell array MCB1 to read or write a signal from or to thedata-line pairs D0tl and D0bl, and D1tl and D1bl. The control signalsSHL10 and SHR2E are set at VSS so that the shared gates SHLG0 and SHRG1separate the memory cell array MCB0 from the sense amplifier part SAB1Oand also the memory cell array MCB2 from the sense amplifier part SAB2Eto perform operations similar to those shown in FIGS. 11 and 12.

As in this exemplary arrangement, when the sense amplifiers arealternately provided at both sides of each memory cell array, the layoutpitch of the sense amplifiers can be mitigated to be doubled. Further,even when the precharge voltages for the data-line pairs in the memorycell array are grouped into two, one set of precharge voltage supplylines, one set of sense amplifier driving lines and one set of I/O linepairs are only required for each sense amplifier part, thus facilitatingits layout. Furthermore, the layout of these control circuits can befacilitated.

Although each one pair of data lines has been connected to the left andright sense amplifier parts in this example, each plural pairs of datalines may be connected thereto.

[Second Embodiment]

An embodiment of realizing aforementioned second means will then beexplained. A major part of its exemplary arrangement is shown in FIG.20. This arrangement is featured in that charge transfer is carried outbetween the data-line pairs precharged to different voltages to performsensing and precharging operations. Precharge circuits PC0S, PC1S, . . .and sense amplifiers SA0S, SA1S, . . . are connected to the data-linepairs D0bS and D0tS, D1bS and D1tS, . . . Meanwhile, the prechargecircuits PC0C, PC1C, . . . and sense amplifiers SA0C, SA1C, . . . areconnected to the data-line pairs D0bC and D0tC, D1bC and D1tC, . . . Theprecharge circuits and sense amplifiers have such circuit arrangement asshown in FIG. 1. The ground voltage VSS is supplied to the prechargecircuits PC0S and PC1S, the source voltage VCC is supplied to theprecharge circuits PC0C and PC0C. NMOS transistors in the senseamplifiers SA0S, SA1S, . . . are connected at their sources to theground voltage VSS, while PMOS transistors in the sense amplifiers SA0C,SA1C, . . . are connected at their sources to the source voltage VCC.For simplicity, I/O lines and I/O gates for data transfer to externaldevices are omitted in the drawing. Reference symbols MCAS and MCACdenote memory cell arrays, which are each arranged, for example, asshown by MCA1 in FIG. 2. Further, symbol CSD denotes a sense amplifierdriving circuit, which performs charge transfer from or to the senseamplifiers SA0S, SA1S, . . . and SA0C, SA1c, . . . by means of switchesprovided in the circuit.

With this exemplary arrangement, the memory cell arrays MCAS and MCACare both activated simultaneously. This operation will be explained byreferring to a timing chart shown in FIG. 21. In the standby state,since the control signal FPC is set at VCH, the NMOS transistors in theprecharge circuits PC0S, PC1S, . . . and PC0C, PC1C, . . . are in theirON state, so that the data-line pairs D0bS and D0tS, D1bS and D1tS, . .. are precharged to VSS and the data-line pairs D0bC and D0tC, D1bC andD1tC, . . . are precharged to VCC. For operation, the control signal FPCcauses the precharge circuits to be turned OFF. Thus, when the word line(W0 in FIG. 21) is set at the voltage VCH at the time of selection, thememory cell is selected and its remanent polarization is read out to thedata line as charge. In this case, the control signal FS causes couplingbetween the sense amplifier driving lines CSPS and CSNC in the senseamplifier driving circuit CSD. This results in that charge transfer iscarried out between the sense amplifiers SA0S, SA1S, . . . and SA0C,SA1C, . . . so that the sense amplifier driving lines CSPS and CSNC areset nearly at the intermediate voltage VCC/2. At this time, the senseamplifier differentially amplifies voltages on the data lines in eachpair to perform its early sense operation. Next, a control signal FAMPcauses the sense amplifier driving line CSPS to be set at VSS while thesense amplifier driving line CSNC to be set at VSS for sensingoperation, whereby one of data lines in each pair is amplified to VSSand the other thereof is amplified to VCC. When the data is externallytransferred under such a condition that the sense amplifier amplifiedthe data, its read operation is carried out. When the voltage of thedata line D is controlled according to data externally provided, writeoperation is carried out. After the word line W0 is lowered, the controlsignal FAMP causes the sense amplifier driving line CSPS and CSNC to befloating. And again, the control signal FS causes coupling between thesense amplifier driving lines CSPS and CSNC. This results in thatcharger transfer is carried out between the sense amplifiers SA0S, SA1S,. . . and SA0C, SA1C, . . . , the sense amplifier driving lines CSPS andCSNC to be set nearly at the intermediate voltage VCC/2, the high levelof the data-line pairs D0bS and D0tS, D1bS and D1tS, . . . as well asthe low level of the data-line pairs D0bC and D0tC, D1bC and D1tC, . . .are both set nearly at VCC/2, thus performing its early prechargeoperation. Next, the control signal FS causes separation between thesense amplifier driving lines CSPS and CSNC, and then the control signalFPC causes the sense amplifier driving line CSPS to be set at VSS, thesense amplifier driving line CSNC to be set at VCC and the prechargecircuit to be turned ON, thus performing its precharge operation andreturning it to the standby state.

Through the aforementioned operations, the early mentioned secondproblem can be solved in such a manner as to be explained below. Priorto the sense and precharge operations of coupling the sense amplifierdriving line with the power source, the early sense and early prechargeoperations based on charge share are carried out. At this time, nocharge transfer is carried out from or to the power source. Since nearlyhalf of the sense and precharge operations is carried out based on thecharge share, the amount of charge consumed for each data line pair isCD×VCC/2. Accordingly, power necessary for charge and discharge of thedata lines is about half of the power necessary for the VSS prechargescheme of the prior art ferroelectric memory device and is equal to thepower of the VCC/2 precharge scheme of DRAM.

Although the charge share between the sense amplifier driving lines hasbeen used for both of the early sense and early precharge operations inthis embodiment, it is possible to employ the charge share for only oneof the operations. For example, when the charge share is used only forthe early precharge operation, the effect of reducing the chargeconsumption drops to half but the delay of the sense operation becomessmall.

FIG. 22 shows a detailed exemplary arrangement of a sense amplifierdriving circuit and a control circuit. This arrangement is used asconnected to the sense amplifier driving line CSN1 and CSP0 of theexemplary arrangement of FIG. 1, and performs an operation correspondingto a combination of the present embodiment and the foregoing firstembodiment. In FIG. 22, reference symbol CSD0 denotes a sense amplifierdriving circuit which drives the sense amplifier driving lines CSN1 andCSP0 according to control signals FS0, FAMP0, and FPC0. Further, symbolCSC0 denotes a control circuit CSC0 for the sense amplifier drivingcircuit, which is made up of delay circuits D1 and D2, inverters andNAND circuits to generate the control signals FS0, FAMP0 and FPC0 fromcontrol signals FSA and FR2b.

The operation of this exemplary arrangement will be explained with useof such a timing chart as shown in FIG. 23. First, when the controlsignal FR2b indicative of a precharge period is set at VSS, the controlsignal FPC0 is set at VSS so that the sense amplifier driving lines CSN1and CSP0 are floating. Next, when the control signal FSA indicative ofthe operational duration of the sense amplifier is set at VCC, thecontrol signal FS0 is set at VCC, the coupling is established betweenthe sense amplifier driving lines CSN1 and CSP0 to perform the earlysense operation. After passage of a time determined by the delay circuitD1, the control signal FS0 is returned to VSS and the control signalFAMP0 is correspondingly returned to VCC to perform the sense operation.And when the control signal FSA is returned to VSS, the control signalFAMP0 is returned to VSS. When the control signal FR2b is set at VCC,the control signal FS0 is set again at VCC so that the coupling isestablished between the sense amplifier driving lines CSN1 and CSP0 toperform the early precharge operation. After passage of a timedetermined by the delay circuit D2, the control signal FS0 is returnedto VSS and the control signal FPC0 is correspondingly set at VCC toperform the precharge operation, returning it to the standby state.

As mentioned above, the control signal FS0 is set at VSS in the controlcircuit CSC to thereby set the control signal FAMP0 or FPC0 at VCC, thusenabling prevention of overlap of the control signal FS0 and FAMP0 orFPC0 and also reduction of a delay caused by a timing margin.

When the early sense operation based of such charge share is combinedwith the first embodiment, the effect of reducing the array noise can begreat. In the early sense operation, the operation of the data-line pairprecharged to VSS as well as the operation of the data-line pairprecharged to VCC take place completely simultaneously and becomesymmetrical with respect to the intermediate voltage VCC/2 as itscenter. For this reason, there is no difference in the drive timing andspeed between the sense amplifiers, thus compensating the array noise.

FIG. 24 shows another exemplary arrangement of the sense amplifierdriving circuit and control circuit. This arrangement is featured inthat a switch for coupling the sense amplifier driving lines has a diodecharacteristic. As in the exemplary arrangement of FIG. 22, thisarrangement is used as connected to the sense amplifier driving linesCSN1 and SCP0 in the exemplary arrangement of FIG. 1. In FIG. 24, symbolCSDL denotes a sense amplifier driving circuit, which drives the senseamplifier driving lines CSN1 and CSP0 according to the control signalsFSA, FAMP1, FPC1 and FSP. Transistors connected to diodes in the senseamplifier driving circuit CSD1 are NMOS transistors having a thresholdvoltage as low as nearly 0. Symbol CSC1 denotes a control circuit forthe sense amplifier driving circuit, which is made up of delay circuitsD1 and D2, inverters, and NAND circuits to generate control signals FSA,FAMP1, FPC1 and FSP from control signals FSA and FR2b.

The operation of this exemplary arrangement will be explained byreferring to such a timing chart as shown in FIG. 25. First, when thecontrol signal FR2b indicative of a precharge duration is set at VSS,the control signal FPC0 is set at VSS. Next, when the control signal FSAindicative of an operational duration of the sense amplifier is set atVCC, the control signal FSAMP is set at VCC so that a current flows fromthe sense amplifier driving line CSN1 to the sense amplifier drivingline CSP0 to perform the early sense operation. After passage of a timedetermined by the delay circuit D1, the control signal FSAMP is returnedto VSS and the control signal FAMP1 is set at VCC to thereby perform thesense operation. And when the control signal FSA is returned to VSS, thecontrol signal FAMP1 is returned to VSS. And when the control signal FSAis returned to VSS, the control signal FAMP1 is returned to VSS. Whenthe control signal FR2b is set at VCC, the control signal FSP is set atVCC, so that a current flows from the sense amplifier driving line CSP0to the sense amplifier driving line CSN1 to perform the early prechargeoperation. After passage of a time determined by the delay circuit D2,the control signal FSP is returned to VSS and the control signal FPC1 isset at VCC to perform the precharge operation, returning it to thestandby state.

Since a diode-connection transistor is inserted in series with atransistor operating as a switch between the sense amplifier drivinglines CSN1 and SCP0, no current flows from the sense amplifier drivingline CSP0 to the sense amplifier driving line CSN1 when the controlsignal FSP is set at VCC; while no current flows from the senseamplifier driving line CSN1 to the sense amplifier driving line CSP0when the control signal FSP is set at VCC. For this reason, the VCCduration of the control signals FSAMP and FAMP1 is overlapped with theVCC duration of the control signals FSP and FPC1, its charge consumptionwill not increase. For this reason, any timing margin becomesunnecessary for the control signals FSAMP and FAMP1, and FSP and FPC1,and thus reduction of the operational speed caused by the early senseand early precharge operations can be minimized. Further, the controlcircuit of the sense amplifier driving circuit can be simplified inconfiguration.

[Third Embodiment]

Explanation will then be made as to an embodiment for realizing theaforementioned third means. A major part of an exemplary arrangement ofthe embodiment is shown in FIG. 26. This arrangement is featured in thatthe precharge voltages of the data lines are switched to VCC and VSS foreach operational cycle. Precharge circuits PC0, PC1, . . . and senseamplifiers SA0, SA1, . . . are connected to data-line pairs D0b and D0t,D1b and D1t, . . . The precharge circuits and sense amplifiers have sucha circuit configuration as shown in FIG. 1. An output of a T flip-flopis supplied as the precharge voltage VPC to the precharge circuits PC0and PC1 through a driving circuit VPD. The driving circuit VPD is madeup of, for example, a plurality of CMOS inverters connected in series.Symbol MCA denotes a memory cell array, which is arranged, e.g., asshown by MCA1 in FIG. 1. For simplicity, I/O lines and I/O gates fordata transfer from or to external devices are omitted in the drawing.

The operation of this exemplary arrangement will be explained byreferring to such a timing chart as shown in FIG. 27. The drawing showswhen the precharge voltage VPC is set at VSS. In the standby state,since the control signal FPC is set at VCH, NMOS transistors in theprecharge circuits PC0, PC1, . . . are put in their ON state so that thedata-line pairs D0b and D0t, D1b and D1t, . . . are precharged to VSS.For operation, the control signal FPC causes the precharge circuits tobe turned OFF. When the word line (W0 in FIG. 27) is set at the voltageVCH at selection, the memory cell is selected and its remanentpolarization is read out to the data line as charge. Next, the controlsignal FSA indicative of an operational duration of the sense amplifiercauses the output of the T flip-flop to be inverted so that theprecharge voltage VPC is set at VSS. Further, the sense amplifierdriving line CSP is set at VCC and the sense amplifier driving line CSNis set at VSS so that the sense amplifiers SA0, SA1, . . .differentially amplify voltages on data lines in each pair. When signaltransfer to or from external devices is carried out under such acondition that the sense amplifier amplifies the signal data, the reador write operation is carried out. After the word line W0 is lowered,the control signal FPC causes the precharge circuits to be turned ON,thus precharging the data-line pairs D0b and D0t, D1b and D1t, . . . toVCC. Further, the sense amplifier driving line CSP is returned tot VSSand the sense amplifier driving line CSN is returned to VCC to stop theoperation of the sense amplifier.

Though not illustrated in the drawing, in a next operational cycle, theprecharge voltage VPC is switched from VCC to VSS so that the data linepair so far precharged is precharged to VSS.

Through the aforementioned operations, the above third problem can besolved in such a manner as to be explained below. The precharge of thedata lines driving the word line is switched to VCC and VSS in eachcycle. Even when attention is directed to a certain word line, the VSSprecharge and VCC precharge are repeated by the same number of VSS andVCC precharge times from the viewpoint of its probability. When a readoperation is carried out in the VSS precharge, the polarization of theferroelectric capacitor having "1" written therein is inverted, andapplication of VCC thereto for rewrite operation causes the polarizationto be again inverted. Meanwhile, the capacitor having "0" so far writtentherein is not inverted. When a read operation is carried out in the VCCprecharge, the polarization of the ferroelectric capacitor having "0" sofar written therein is inverted, and application of VSS for rewritingcauses the polarization to be again inverted. Meanwhile, the capacitorhaving "1" so far written therein is not inverted. Since the number ofreversal writes of the memory cell is usually smaller than the number oftimes of selection of the word line, it is considered the same data isrepetitively sensed and rewritten. That is, it is considered that thereversal and non-reversal operations are repeated. As a result, thefatigue of the ferroelectric capacitor can be suppressed. Further,imprint can be prevented. Accordingly, the deterioration of theferroelectric capacitor can be suppressed and the endurance of theferroelectric memory device can be improved.

In particular, when the insulating film of the ferroelectric capacitoris made of PZT, this is effective. As explained in IEEE InternationalSold-State Circuit Conference, Digest of Technical Papers, pp. 68-69,Feb., 1995,PZT is advantageous in its large remanent polarization but isdisadvantageous in its large fatigue influence. Since the present schemecan suppress the deterioration, it can make the most of the PZT'sadvantage of the large remanent polarization.

Though omitted in the drawing, the present scheme is especially validwhen the reverse polarization is used in the dummy cell for generating areference voltage. The dummy cell used in the reverse polarization is,as disclosed in JP-A-2-110893, made up of a ferroelectric capacitor forreverse polarization and a ferroelectric capacitor for no reversepolarization. When the present scheme is employed, the ferroelectriccapacitors in the dummy cell can repeat reversal and non-reversal of thepolarization, thus suppressing the deterioration.

In the operation of FIG. 27, in the standby state, the sense amplifierdriving line CSN is set at VCC and the sense amplifier driving line CSPis set at VSS so that the same control can be performed over the senseamplifier driving lines regardless of the precharge voltages. Therebythe arrangement of the control circuit of the sense amplifier drivinglines can be simplified.

Though the T flip-flop has been used to switch the precharge voltages ineach cycle in this embodiment, a counter may be used to switch them oneach plural-cycle basis. Further, a timer may be used to switch them atintervals of a constant time. When the switching frequency is madesmall, the effect of suppressing the deterioration of the ferroelectriccapacitor becomes small, but the power consumption necessary forcharge/discharge of the precharge voltages of the supply lines can bemade small.

FIG. 28 is an exemplary arrangement of a combination with the firstembodiment, which is featured in that precharge voltages of data linepairs in the memory cell array are grouped into two of VSS and VCC andthe voltage switching is carried out in each cycle. Precharge circuitsPC0, PC1, . . . and sense amplifiers SA0, SA1, . . . are connected todata-line pairs D0b and D0t, D1b and D1t, . . . A precharge voltage VPC0is connected to the precharge circuits PC0 and PC2, while the prechargevoltage VPC1 is connected to the precharge circuits PC1 and PC3. Forsimplicity, I/O lines and I/O gates for data transfer from or toexternal devices are omitted in the drawing. The operation of thisexemplary arrangement will be explained by referring to such a timingchart as shown in FIG. 29. The timing chart shows when the prechargevoltage VPC0 is set at VSS and the precharge voltage VPC1 is set at VCC.In the standby state, the precharge circuits PC0, PC1, . . . cause thedata-line pair D0b and D0t to be precharged to VSS and the data-lienpair D1b and D1t to be precharged to VCC. The control signal FPC causesthe precharge circuits to be turned OFF and the word line (W0 in FIG.29) to be set at the sleeted-word-line voltage VCH, so that the memorycell is selected and its remanent polarization is read out to the dataline as charge. Further, the sense amplifier driving line CSP0 is set atVCC and the sense amplifier driving line CSN1 is set at VSS todifferentially amplify the voltages of the data lines in each pair. Reador write operation is carried out when signal transfer from or toexternal devices is carried out under such a condition that the senseamplifier amplifies the data. At this time, the precharge voltage VPC0is set at VCC while the precharge voltage VPC1 is set at VSS. After theword line W0 is lowered, the control signal FPC causes the prechargecircuits to be turned ON and the data-line pair D0b and D0t to beprecharged to VCC and the data-line pair D1b and D1t to be precharged toVSS. Further, the sense amplifier driving line CSP1 is returned to VSSand the sense amplifier driving line CSN0 is returned to VCC to stop theoperation of the sense amplifier.

Though not illustrated, in the next operational cycle, the prechargevoltage VPC0 is switched from VCC to VSS and the precharge voltage VPC1is switched from VSS to VCC, so that the data-line pair so farprecharged to VCC is precharged to VSS and the data-line pair so farprecharged to VSS is precharged to VCC.

Due to the above operations, compatibility can be realized between theeffects of the first and third embodiments. In other words, the arraynoise can be reduced to improve the S/N ratio, and the deterioration ofthe ferroelectric capacitor can be suppressed to improve its endurance.

FIG. 30 shows an exemplary arrangement of a sense amplifier drivingcircuit. This arrangement is used as connected to the sense amplifierdriving lines CSN0, CSN1, CSP0 and CSP1 of the exemplary arrangement ofFIG. 28 to perform operation corresponding to the combined operation ofthe present embodiment, above first and second embodiments. In FIG. 30,symbol CSD2 denotes a sense amplifier driving circuit, which drives thesense amplifier driving lines CSN0, CSN1, CSP0 and CSP1 according tocontrol signals FS2, FS3, FAMP2, FAMP3, FPC2 and FPC3.

The operation of this exemplary arrangement will be explained with useof such a timing chart as shown in FIG. 31. As in FIG. 29, this timingchart shows when the precharge voltage VPC0 is set at VSS and theprecharge voltage VPC1 is set at VCC. First, the control signal FPC2 isset at VSS so that the sense amplifier driving lines CSN1 and CSP0 arefloating. Next, the control signal FS2 is set at VCC so that thecoupling is established between the sense amplifier driving lines CSN1and CSP0 to perform the early sense operation. The control signal FS0 isreturned to VSS and the control signal FAMP2 is correspondingly returnedto VCC so that the sense amplifier driving line CSN1 is set at VSS andthe sense amplifier driving line CSP0 is set at VCC to perform the senseoperation. And the control signal FAMP3 is returned to VSS and thecontrol signal FS3 is set at VCC so that the coupling is realizedbetween the sense amplifier driving lines CSN0 and CSP1 to perform theearly precharge operation. The control signal FS3 is returned to VSS andthe control signal FPC3 is correspondingly returned to VCC to performthe precharge operation.

In this way, the early sense and early precharge operations based oncharge share enable simultaneous acquirement of the effect of the secondembodiment together with the effects of the first and third embodiment.That is, the array noise can be reduced to improve the S/N ratio, thedeterioration of the ferroelectric capacitor can be suppressed toimprove its endurance, and the charge consumption necessary forcharge/discharge of the data lines can be reduced to reduce powerconsumption.

FIGS. 32 and 33 show an exemplary arrangement when a sense amplifier isprovided at both sides of a memory cell array. The arrangement isfeatured in that precharge voltages are switched by shared gates. Whencompared with the exemplary arrangement of FIGS. 16 and 17 wherein asense amplifier is provided at both sides of the memory cell array inthe first embodiment, this arrangement is different in that a senseamplifier is shared by a twice as many number of data-line pairs due toshared gates. Symbols MCB0, MCB1, MCB2, . . . denote memory cell arrays,which are each arranged, for example, as shown by MCA1 in FIG. 2. Senseamplifier parts SAC0E, SAC1O, SAC2E, SAC3), . . . are provided betweentwo memory cell arrays as shared thereby; and the sense amplifier partsprovided at both sides of each memory cell array perform the senseoperation. Further, a column decoder YDEC is commonly provided topluralities of memory cell arrays and sense amplifier parts, and columnselect lines YS (such as YS0) are extended on the memory cell arrays.The inter-connection of the sense amplifier parts is repeated on each2-amplifier-part basis. The sense amplifier part SAC1O is arranged asshown in FIG. 32, the sense amplifier part SAC2E is arranged as shown inFIG. 33, the sense amplifier and the precharge circuit are provided forevery two data-line pairs as connected by the shared gates. SymbolsSHLG0O, SHLG1O, SHRG0O, SHRG1O, SHLG0E, SHLG1E, SHRG0E and SHRG1E denoteshared gates, symbols IOG0 and IOG1 denote I/O gates, which have suchcircuit configurations as shown in FIG. 9. Symbols PC0 and PC1 denoteprecharge circuits, symbols SA0 and SA1 denote sense amplifiers, whichhave such circuit configurations as shown in FIG. 1. The ground voltageVSS is supplied to the precharge circuit PC0, while the source voltageVCC is supplied to the precharge circuit PC1.

The read and write operations are carried out as shown in FIGS. 34 and35 respectively. The drawings show when the word line W0 is selected inthe memory cell array MCB1 to read or write signals from the data-linepair D0tl and D0bl so far precharged to VSS and from the data-line pairD1tl and D1bl so far precharged to VCC. In the standby state, thedata-line pair D0tl and D0bl are coupled with the precharge circuit PC0and sense amplifier SA0 in the sense amplifier part SAC1O, while thedata-line pair D1tl and D1bl are coupled with the precharge circuit PC1and sense amplifier SA1 in the sense amplifier part SAC2E. First, thecontrol signals SHL1O0 and SHR2E0 are set at VSS so that the sharedgates SHLG0E and SHRG0E cause the memory cell array MCB0 to be separatedfrom the sense amplifier part SAC1O and the memory cell array MCB2 to beseparated from the sense amplifier part SAC2E. Next, as in the operationshown in FIGS. 18 and 19, the sense operation, read or write operation,and rewrite operation are carried out. After the word line W0 isreturned to VSS, the control signals SHR1O0 and SHL2E1 are set at VSS sothat the shared gates SHRG0O and SHLG1E cause the data-line pairs D0tland D0bl, and D1tl and D1bl to be separated from the sense amplifierparts. And the sense amplifier driving line CSN1O is set at VCC and thesense amplifier driving line CSP2E is set at VSS to stop the operationof the sense amplifiers SA0 and SA1. Then the control signals SHR1O1 andSHL2E0 are set at VSS so that the shared gate SHRG1O and SHLG0E causecoupling of the data-line pairs D0tl and D0bl, and D1tl and D1bl withthe sense amplifier part provided on the opposite side, the controlsignals FPC1O and FPC2E are set at VCC to perform the prechargeoperation. Thereby the data-line pair D0tl and D0bl is precharged to VCCand the data-line pair D1tl and D1bl is precharged to VSS.

Though not illustrated, in the next operational cycle, through theswitching of the control signals of the shared gates, the data-line pairso far precharged to VCC is precharged to VSS, while the data-line pairso far precharged to VSS is precharged to VCC.

With this exemplary arrangement, compatibility can be establishedbetween the effects of the exemplary arrangement of FIGS. 17 and 18 andthe high-endurance effect of the third embodiment. In addition, evenwhen the precharge of the data-line pairs is switched, the prechargevoltage of the sense amplifier part is made constant, whereby theprecharge circuits and sense amplifiers can be easily controlled.Further, it is unnecessary to perform switching of supply line voltagesfor precharge voltages.

In the foregoing, the first to third embodiments have been explained inconnection with the various exemplary arrangements and operationaltiming charts. The present invention is not limited only to the aboveexplained arrangements but also may be modified in various ways in arange not departing from the gist of the invention. For example, thoughthe explanation has been made in connection with the case where thesource voltage VCC and ground voltage VSS are used as write voltages,internal supply voltages generated in a voltage down converter, etc.within a chip may be instead used. In this case, device reliability canbe secured with a high reliability independently of an external supplyvoltage. The voltage to be used for the precharge is not required tocoincide with the write voltage, and any precharge voltage may beemployed so long as it causes a change of the polarization status of theferroelectric capacitor at the time of selection of a memory cell. Forexample, the precharge voltage can be set so that a difference of theprecharge voltage from the plate voltage is larger than that of thewrite voltage therefrom. In this case, even when the ferroelectriccapacitor has a large capacitance, the application voltage to the senseamplifier driving line can be set to have a sufficient magnitude, since,during driving of the word line, compensating the charge in thecapacitance of the data line shared with the capacitance of theferroelectric capacitor. Further, the voltage to be applied to the senseamplifier driving line is not required to coincide with the writevoltage and any voltage may be employed so long as it causes the dataline voltage to be set at a desired write voltage. For example, thevoltage applied to the sense amplifier driving line can be set to betemporarily larger than such a level that a difference from theprecharge voltage is larger than the write voltage, and, when the dataline voltage comes near the write voltage, can be set at the writevoltage. In this case, the voltage difference applied to the senseamplifier can be made large to speed up the amplifying operation of thesense amplifier.

Further, the precharge circuit and sense amplifier may have variouscircuit configurations. For example, even when a transistor equalizingthe data line pair is removed from the precharge circuit, it canoperate. The sense amplifier always operating in the VCC precharge modemay also comprise such an NMOS sense amplifier as used in the VCCprecharge DRAM. Similarly, the sense amplifier always operating in theVSS precharge mode may comprise only PMOS transistors. Further, thememory cell may also made up of ferroelectric capacitors and PMOStransistors.

As has been explained in the foregoing, in accordance with the presentinvention, the problem of the ferroelectric memory that the VCC/2precharge scheme widely used in DRAM cannot be employed, can be solved.That is, when the precharge voltages are previously grouped for eachdata line in the memory cell array, the array noise can be reduced toimprove the S/N ratio. Further, when the charge share between thedata-line pairs precharged to different voltages is employed, chargeconsumption necessary for charge/discharge of the data lines can bedecreased to reduce power consumption. Furthermore, when the prechargevoltages of the data-line pair are switched according to the operationalcycle, the deterioration of the ferroelectric capacitor can besuppressed with a high endurance.

We claim:
 1. A ferroelectric memory device including first and secondmemory cells each having a ferroelectric capacitor with an insulatingfilm of ferroelectric material and having a transistor connected to oneof electrodes of the ferroelectric capacitor, a first data lineconnected to said transistor of said first memory cell, a second dataline connected to said transistor of said second memory cell, word linesconnected to control electrodes of the transistors of said first andsecond memory cells, and first and second sense amplifiers provided asassociated with said first and second data lines; characterized bycomprising:a first precharge circuit for connecting said first data lineto a first precharge potential prior to selection of said word lines;and a second precharge circuit for connecting said second data line to asecond precharge potential prior to selection of said word lines;andcharacterized in that a potential of the other electrodes of saidferroelectric capacitors of said first and second memory cells is set tobe between said first and second precharge potentials.
 2. Aferroelectric memory device as set forth in claim 1, characterized inthat a difference between the potential of the other electrodes of saidferroelectric capacitors of said first and second memory cells and saidfirst precharge potential is equal to a difference between the potentialof the other electrode of said ferroelectric capacitors of said firstand second memory cells and said second precharge potential.
 3. Aferroelectric memory device including first and second memory cells eachhaving a ferroelectric capacitor with an insulating film offerroelectric material and having a transistor connected to one ofelectrodes of the ferroelectric capacitor, a first pair of data linesone of which is connected to said transistor of said first memory cell,a second pair of data lines one of which is connected to said transistorof said second memory cell, a word line connected to control electrodesof the transistors of said first and second memory cells, and first andsecond sense amplifiers provided as associated with said first andsecond pairs of data lines; characterized by comprising:a firstprecharge circuit for connecting said first data line pair to a firstprecharge potential prior to selection of said word line; and a secondprecharge circuit for connecting said second data line pair to a secondprecharge potential prior to selection of said word line;andcharacterized in that a potential of the other electrodes of saidferroelectric capacitors of said first and second memory cells is set tobe between said first and second precharge potentials.
 4. Aferroelectric memory device as set forth in claim 3, characterized inthat a difference between the potential of the other electrodes of saidferroelectric capacitors of said first and second memory cells and saidfirst precharge potential is equal to a difference between the potentialof the other electrode of said ferroelectric capacitors of said firstand second memory cells and said second precharge potential.
 5. Aferroelectric memory device as set forth in any of claim 1 to 4,characterized in that said first precharge potential is the same as afirst write voltage indicative of data "1" when data is written in saidfirst memory cell, and said second precharge potential is the same as asecond write voltage indicative of data "0" when data is written in saidfirst memory cell.
 6. A ferroelectric memory device as set forth in anyof claim 1 to 4, characterized in that transistors in said firstprecharge circuit have a conduction type channel opposite to that oftransistors in said second precharge circuit.
 7. A ferroelectric memorydevice including first to fourth memory cells each having aferroelectric capacitor with an insulating film of ferroelectricmaterial and having a transistor connected to one of electrodes of theferroelectric capacitor, a first pair of data lines one of which isconnected to said transistor of said first memory cell, a second pair ofdata lines one of which is connected to said transistor of said secondmemory cell, a third pair of data lines one of which is connected tosaid transistor of said third memory cell, a fourth pair of data linesone of which is connected to said transistor of said fourth memory cell,first word lines connected to control electrodes of the transistors ofsaid first to fourth memory cells, and first to fourth sense amplifiersprovided as associated with said first to fourth data lines;characterized by comprising:a first precharge circuit for connectingsaid first and third data line pairs to a first precharge potentialprior to selection of said first word lines; a second precharge circuitfor connecting said second and fourth data line pairs to a secondprecharge potential prior to selection of said first word lines; a firstI/O line pair provided commonly to said first and third data line pairs;and a second I/O line pair provided commonly to said second and fourthdata line pairs;and characterized in that a potential of the otherelectrodes of said ferroelectric capacitors of said first to fourthmemory cells is set to be between said first and second prechargepotentials.
 8. A ferroelectric memory device as set forth in claim 7,characterized in that a difference between the potential of the otherelectrodes of said ferroelectric capacitors of said first to fourthmemory cells and said first precharge potential is equal to a differencebetween the potential of the other electrode of said ferroelectriccapacitors of said first to fourth memory cells and said secondprecharge potential.
 9. A ferroelectric memory device as set forth inany of claim 7 or 8, characterized in that said first prechargepotential is the same as a first write voltage indicative of data "1"when data is written in said first memory cell, and said secondprecharge potential is the same as a second write voltage indicative ofdata "0" when data is written in said first memory cell.
 10. Aferroelectric memory device as set forth in any of claim 7 or 8,characterized in that transistors in said first precharge circuit have aconduction type channel opposite to that of transistors in said secondprecharge circuit.
 11. A ferroelectric memory device as set forth in anyof claims 7 or 8, characterized by further comprising:ninth to twelfthmemory cells each including a ferroelectric capacitor with an insulatingfilm of ferroelectric material and including a transistor connected toone of electrodes of the ferroelectric capacitor; a fifth pair of datalines one of which is connected to said transistor of said ninth memorycell; a sixth pair of data lines one of which is connected to saidtransistor of said tenth memory cell; a seventh pair of data lines oneof which is connected to said transistor of said eleventh memory cell;an eighth pair of data lines one of which is connected to saidtransistor of said twelfth memory cell; second word lines connected tocontrol electrodes of transistors of said ninth to twelfth memory cells;fifth to eighth sense amplifiers provided as associated with said fifthto eighth data line pairs respectively; a third precharge circuit forconnecting said fifth and seventh data line pairs to said firstprecharge potential prior to selection of said second word lines; afourth precharge circuit for connecting said sixth and eighth data linepairs to said second precharge potential prior to selection of saidsecond word lines; a third I/O line pair provided commonly to said fifthand seventh data line pairs; a fourth I/O line pair provided commonly tosaid sixth and eighth data line pairs; a first control line forconnecting said first data line pair to said first I/O line pair and forconnecting said fifth data line pair to said third I/O line pair; and athird control line for connecting said second data line pair to saidfirst I/O line pair and for connecting said seventh data line pair tosaid third I/O line pair; characterized in that said first and third I/Oline pairs are precharged to said first precharge voltage, and saidsecond and fourth I/O line pairs are precharged to said second prechargevoltage.
 12. A ferroelectric memory device as set forth in any of claims7 or 8, characterized in that said first to fourth data line pairs areprovided between said first and third sense amplifiers and said secondand fourth sense amplifiers.
 13. A ferroelectric memory device as setforth in any of claims 1 to 4, 7, or 8, characterized in that saidferroelectric material is PZT.
 14. A ferroelectric memory device as setforth in claim 3, characterized in that said first and second pairs ofdata lines have a pair of input lines and a pair of output lines incommon.
 15. A ferroelectric memory device as set forth in claim 14,characterized by further comprising:a first output gate provided betweensaid first pair of data lines and said pair of output lines; and asecond output gate provided between said second pair of data lines andsaid pair of output lines, and characterized in that a threshold voltageof MOS transistors in said first output gate is different from athreshold voltage of MOS transistors in said second output gate.
 16. Aferroelectric memory device as set forth in any one of claims 3 or 4,wherein said first and second memory cells each have a secondferroelectric capacitor and a second transistor connected to one ofelectrodes of the second ferroelectric capacitor;the second transistorin said first memory cell being connected to the other data line of saidfirst data line pair; the second transistor in said second memory cellbeing connected to the other data line of said second data line pair;control electrodes of said second transistors in said first and secondmemory cells being connected to said word line; and potentials of theother electrodes of said second ferromagnetic capacitors in said firstand second memory cells being between said first and second prechargepotentials.
 17. A ferroelectric memory device as set forth in any one ofclaims 7 or 8, wherein said first to fourth memory cells each have asecond ferroelectric capacitor and a second transistor connected to oneof electrodes of the second ferroelectric capacitor;the secondtransistor in said first memory cell being connected to the other dataline of said first data line pair; the second transistor in said secondmemory cell being connected to the other data line of said second dataline pair; the second transistor in said third memory cell beingconnected to the other data line of said third data line pair; thesecond transistor in said fourth memory cell being connected to theother data line of said fourth data line pair; control electrodes ofsaid second transistors in said first to fourth memory cells beingconnected to said word line; potentials of the other electrodes of saidsecond ferromagnetic capacitors in said first to fourth memory cellsbeing between said first and second precharge potentials.
 18. Aferroelectric memory device as set forth in any of claims 14 or 15,characterized in that said ferroelectric material is PZT.